1. Field of the Invention.
The present invention relates to a data transfer control interface circuit and, more particularly, to an interface circuit for controlling data transfer by sending an interrupt from a peripheral device to a host and transferring data between the host and the peripheral device.
2. Description of Related Art.
In personal computer systems, AT interfaces are widely adopted to connect a host and its peripheral devices. A hard disk drive (HDD) is one of the typical peripheral devices. The manufacturers of peripheral devices desire standardized data transfer between a host and its peripheral devices through the AT interface. However, in some hosts, several operating sequences are possible depending on commands. For example, a read command to the HDD is executed according to when the host reads the status register of the HDD in either of two operating sequences. During a first operating sequence, referred to as the prereading mode, the HDD makes the data request (DRQ) bit of its status register high. At the same time the HDD asserts an interrupt request (IRQ) to the host when the HDD is ready for transferring data (normally data corresponding to one sector) to the host.
When the host receives the IRQ from the HDD, the host first reads the status register of the HDD. At this time, the IRQ is reset, i.e., dropped. Further, the IRQ is always reset when the host reads the status register. Thereafter, the host starts transferring data. When the transfer of data corresponding to one sector is completed, the HDD will reset the DRQ once. This process is repeated until the data has transferred.
The above-described sequence is referred to as prereading mode since the host reads the status register before data is transferred. However, there are some cases in which a read command is processed differently. The second sequence will hereinafter be referred to as "postreading (second mode)" because a host reads a status register after data transfer corresponding to one sector is completed.
The HDD makes the data request (DRQ) bit of its status register high and at the same time asserts an interrupt request (IRQ) to the host when the HDD is ready for transferring data (normally data corresponding to one sector) to the host. If a host receives an IRQ from a HDD, the host first starts transferring sector data and transfers it until the sector end. When the transfer of data corresponding to one sector is completed, the HDD will reset the DRQ once. The host reads the status register of the HDD. This resets the IRQ. However, there are some cases in which the IRQ is reset concurrently when the DRQ is reset. These steps are repeated until the data is transferred.
When the host is operated in the postreading mode, there is a case in which an erroneous operation occurs. This error occurs when the host reads the status register of the HDD to determine whether a current sector status is later than when the HDD is ready for the next sector. In this case, the next IRQ is reset by the reading of the status register in the previous sector transfer. Thus, the host continues to wait for the IRQ of the next sector and the HDD continues to wait for data transfer. Since the IRQ of the next sector is accessed by hardware as soon as sector data is ready, this problem occurs often.
To avoid the above-described abnormal situation, the IRQ of the next sector must be asserted after the host has read the status register. However, if the IRQ is merely delayed, data transfer performance becomes deteriorated when the host is in the prereading mode. Therefore, on the one hand in the prior art, a method is taken in which a switch is set according to whether the host is in the prereading mode or in the postreading mode.
In the postreading mode, the IRQ is not delayed but is again asserted immediately when the status register is read. This prevents deterioration of performance in the case of postreading. However, there are many cases where the latest host is in the prereading mode or in the postreading mode, depending upon the operating system. For example, in OS/2, the host is in the prereading mode and, in an ordinary DOS, the host is in the postreading mode. In such cases, a switch must be set each time the mode changes.
On the other hand, there is also a method in which IRQ is controlled with a microcode. In this method since the timing is delayed at all times (when the IRQ is asserted) both the prereading mode and the postreading mode are operated normally, but the performance is bad compared with the case where hardware control is used.
In order to overcome the above-described problems, an interface circuit which automatically detects whether a host is a prereading mode or a postreading mode, has been proposed in a Japanese Patent Application No. HEI 3-3379, which is a prior application of the present applicant, and which is incorporated by reference herein. This interface circuit comprises a mode detection circuit, a delay circuit and an interrupt request generation circuit. The mode detection circuit automatically detects the mode of a host in accordance with the status of a data request signal DRQ from the controller of a HDD and with the status of an IRQ signal to be sent to the host. The delay circuit delays the DRQ by a predetermined time when the host is in the postreading mode. The interrupt request generation circuit generates an IRQ to be sent to the host in response to an output of the delay circuit (controlled DRQ). When the mode detection circuit detects that the host is the prereading mode, the delay circuit is not operated and the DRQ is supplied as a controlled DRQ to the interrupt request generation circuit without delay.
When the above-described interface circuit is employed, the operating performance will be improved compared with the conventional method of converting with a switch and the method of controlling with a microcode. However, since the delay time of the DRQ is determined in advance, there is the problem that, even if the status reading by the host is completed before the determined delay time elapses, the IRQ could not be output immediately.
In consideration of the above-described problem, the present applicant has proposed in a Japanese Application No. HEI 4-264371, herein incorporated by reference, an interface circuit for controlling data transfer. The interface circuit includes an interrupt generation circuit, a postreading mode detection circuit and an interrupt bias circuit. The interrupt generation circuit generates an IRQ signal that is sent to a host in response to a DRQ from a controller. The interrupt generation circuit drops the IRQ when status is read by the host. The postreading mode detection circuit for receiving the DRQ and IRQ generates a postreading signal that indicates that the host is in a postreading mode when detecting that the IRQ remains generated after the DRQ is dropped. The interrupt bias circuit, in response to the postreading signal and the status reading of the host, generates a new IRQ by biasing the interrupt request generation circuit.
Thus, since, in response to the postreading signal and the status reading of the host, a new IRQ is generated by biasing the interrupt request generation circuit, the next interrupt request can immediately be generated if status reading occurs when the host is in the postreading mode.
In addition to the above-described prereading and postreading, the operating sequence in which the read command to the HDD is executed has a third mode in which a host reads the status register of a HDD before and after data transfer. This mode is also referred to the both-reading mode.
However, in the above-described conventional interface circuit for controlling data transfer, the interface circuit cannot cope with the both-reading mode since the generation of the IRQ to be asserted to the host is controlled in response to the DRQ from the controller when the host is in both the prereading mode and the postreading mode.
It can be seen then that there is a need to provide an interface circuit for managing data transfer by controlling an interrupt request that is sent to a host in a prereading mode, a postreading mode, and a both-reading mode.